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Sistema e gerenciamento de telecomunicações

Volume 8, Emitir 2 (2019)

Comunicação curta

MMSE Partially Connected Hybrid Beam Forming in MIMO-OFDM Systems

Lenin SB, N Tamilarasan and S Malarkkan

Traditionally, Multi Input Multi Output-Orthogonal Frequency Division Multiplexing (MIMO-OFDM) technique is utilized to increase the diversity gain and to suppress the Inter Carrier Interference (ICI) to some extent. The problem of the existing system is to solve the sum rate maximization due to non-convexity. This paper aims to minimize the computational cost at the transceiver side and improve the spectral efficiency. This paper presents a minimum mean square error (MMSE) approach for partially connected Hybrid beam forming (HBF) weighted sum rate maximization.
Since the feedback of the BF system is more complicated, one-bit training is used to minimize the complications rather than a large bit training method. The paper gives more attention on BF technique for an IEEE802.11ad standard to transmit and receive the data. The proposed method focuses on the reduction of the complexity level, increases the spectral and power efficiency with an optimal number of radio frequency (RF) links. The MMSE estimation validates the results by comparing with various methods such as analog BF and fully digital in terms of loss calculation, sum
rate and normalized MSE. The analysis results are showed that MMSE attains optimal spectral and power efficiency.

Comunicação curta

Performance Analysis of Array Multipliers Using Different Logic Configurations

Swetha BN and Satish Kumar B

Power and speed are the two important design aspects that impact the designing of any circuits. One of the most widely used arithmetic operations in digital circuits is multiplication. There are different multipliers designed depending on the speed and the hardware. There are different technologies with different features. In this paper 4-bit and 8-bit array multipliers are been designed using different designing techniques. The multipliers are designed using CMOS logic configuration, pseudo-NMOS logic configuration and transmission gate logic configuration and are compared in terms of power and delay. The power delay product (PDP) gives the overall performance of the Multipliers.

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